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AMD Zen 4 in 5 nm: Genoa 96, Zen 4c with Bergamo also 128 cores

After the Instinct MI200, AMD delivered a surprise at the Accelerated Data Center premiere: a preview of the Gen4 for servers in the Genoa and Bergamo format. Based on this, Epyc is expected to deliver 96 cores early in 2022 and then 128 cores as a cloud special model in the first half of 2023.

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96: Genoa’s “Core Count” becomes official

While much information about the unofficial has been known about Genoa recently, AMD now officially puts it on the table: up to 96 cores, DDR5 and PCIe 5.0 are the primary products, and support for CXL’s interconnect. TSMC takes the production of CPU chips at an optimal 5 nm output according to AMD, which may speak in favor of the N5P process step. With the new process alone, AMD promises 25 percent higher performance and double the efficiency and packing density.

Zen 4 at 5 nm, presumably TSMC N5P
Zen 4 at 5 nm, presumably TSMC N5P
Zen 4 at 5 nm, presumably TSMC N5P
Zen 4 at 5 nm, presumably TSMC N5P

Genoa is on schedule, currently being tested with partners and should fully follow in the footsteps of regular previous Epyc processors in 2022.

AMD Epyc with Genoa will be the first 5 nm Zen 4 product and will release up to 96 cores in 2022
AMD Epyc with Genoa will be the first 5 nm Zen 4 product and will release up to 96 cores in 2022

Bergamo with Gen 4c with more cores, but less cache

For the first time today AMD is naming an additional new product that is interesting: Bergamo. AMD plans to deliver this CPU with 128 cores in the first half of 2023. According to AMD, the Bergamo 128 is equipped with “Zen 4c” cores, which are software-compatible with “Zen 4” and optimized for configurations with a large number of cores for cloud-native workloads that benefit from maximum thread density. The processor is compatible with Genoa, which finds its place in the same large socket called SP5 with 6,096 contact areas.

Bergamo is an Epyc CPU
Bergamo is an Epyc CPU

In order to meet the increased space requirement of 128 cores compared to Genoa, savings were made in the temporary storage in the chip sets, of which there are still 8 cores. Not sure how much cache is missing. On the same 8-core compute dice, 16 chips are required, i.e. eight instead of six on the top and bottom of the I / O tie. CEO Dr. Lisa Su, however, effectively hid and pointed out that it would be right during the presentation.

16 chips in bergamot should have 8 cores, but less cache
16 chips in bergamot should have 8 cores, but less cache

New Epyc CPUs with Milan X architecture, Gen 3 cores and a 768 MB L3 cache per 3D V cache attached to a socket may not be a distant dream of the future, but will be available from the 1st quarter of 2022.

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